TC74VHCT74AF_07 Datasheet, PDF (1/8 Pages) Toshiba Semiconductor – Dual D-Type Flip-Flop with Preset and Clear

TC74VHCT74AF/AFN/AFT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT74AF,TC74VHCT74AFN,TC74VHCT74AFT
Dual D-Type Flip-Flop with Preset and Clear
The TC74VHCT74 is an advanced high speed CMOS D-FLIP
FLOP fabricated with silicon gate C²MOS technology. It achieves
the high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining the CMOS low power dissipation.
The signal level applied to the D INPUT is transferred to Q
OUTPUT during the positive going transition of the CK pulse.
CLR and PR are independent of the CK and are
accomplished by setting the appropriate input low.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can
be applied to the input and output ^(Note) pins without regard to
the supply voltage. These structure prevents device destruction
due to mismatched supply and input/output voltages such as
battery back up, hot board insertion, etc.
Note: V_CC = 0 V
Features
• High speed: f_max = 160 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 2 μA (max) at Ta = 25°C
• Compatible with TTL outputs: V_IL = 0.8 V (max)
V_IH = 2.0 V (min)
• Power down protection is provided on all inputs and outputs
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Pin and function compatible with the 74 series
(74AC/HC/F/ALS/LS etc.) 74 type.
Note: The JEDEC SOP (FN) is not available in
Japan.
TC74VHCT74AF
TC74VHCT74AFN
TC74VHCT74AFT
Weight
SOP14-P-300-1.27A
SOL14-P-150-1.27
TSSOP14-P-0044-0.65A
: 0.18 g (typ.)
: 0.12 g (typ.)
: 0.06 g (typ.)
1
2007-10-01