TC74VHCT139AF_07 Datasheet, PDF (1/9 Pages) Toshiba Semiconductor – Dual 2-to-4 Line Decoder

TC74VHCT139AF/AFN/AFT/AFK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT139AF,TC74VHCT139AFN,TC74VHCT139AFT,TC74VHCT139AFK
Dual 2-to-4 Line Decoder
The TC74VHCT139A is an advanced high speed CMOS 2 to 4
LINE DECODER/DEMULTIPLEXER fabricated with silicon
gate C²MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The active low enable input can be used for gating or it can be
used as a data input for demultiplexing applications.
When the enable input is held High, all four outputs are fixed
at a high logic level independent of the other inputs.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can
be applied to the input and output ^(Note) pins without regard to
the supply voltage. These structure prevents device destruction
due to mismatched supply and input/output voltages such as
battery back up, hot board insertion, etc.
Note: V_CC = 0 V
Features
• High speed: t_pd = 5.0 ns (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• Compatible with TTL outputs: V_IL = 0.8 V (max)
V_IH = 2.0 V (min)
• Power down protection is provided on all inputs and outputs.
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Low noise: V_OLP = 0.8 V (max)
• Pin and function compatible with the 74 series
(74AC/HC/F/ALS/LS etc.) 139 type.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74VHCT139AF
TC74VHCT139AFN
TC74VHCT139AFT
TC74VHCT139AFK
Weight
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
VSSOP16-P-0030-0.50
: 0.18 g (typ.)
: 0.13 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
1
2007-10-01