TC74HCT139AP_07 Datasheet, PDF (1/8 Pages) Toshiba Semiconductor – Dual 2-to-4 Line Decoder

TC74HCT139AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HCT139AP,TC74HCT139AF,TC74HCT139AFN
Dual 2-to-4 Line Decoder
The TC74HCT139A is a high speed CMOS 2-to-4 LINE
DECODER/DEMULTIPLEXER fabricated with silicon gate
C²MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
The active low enable input can be used for gating or it can be
used as a data input for demultiplexing applications.
When the enable input is held “H”, all four outputs are fixed at
a high logic level independent of the other inputs.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: t_pd = 17 ns (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• Compatible with TTL outputs: V_IH = 2 V (min)
V_IL = 0.8 V (max)
• Wide interfacing ability: LSTTL, NMOS, CMOS
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Pin and function compatible with 74LS139
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HCT139AP
TC74HCT139AF
TC74HCT139AFN
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
1
2007-10-01