TC74HC652AP_07 Datasheet, PDF (1/9 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic Octal Bus Transceiver/Register (3-state)

TC74HC652AP
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC652AP
Octal Bus Transceiver/Register (3-state)
The TC74HC652A is high speed CMOS OCTAL BUS
TRANSCEIVER/REGISTER fabricated with silicon gate CMOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
This device is bus transceiver with 3-state outputs, D-type
flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the internal registers.
When the enable input GAB and GBA are held high, the A1
thru A8 become inputs and the B1 thru B8 become outputs. When
the GAB and GBA are held low, the A1 thru A8 become output
Weight : 1.50 g (typ.)
and the B1 thru B8 become inputs. When GAB is low and GBA
is high, the outputs functions of the A and B Busses are disabled.
The select inputs (SAB, SBA) can multiplex sort and real-time (transparent mode) data.
Data on the A Bus or B Bus can be clocked into the registers on the positive going transition of either CAB or
CBA clock inputs, respectively.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features (Note 1) (Note 2)
• High speed: f_max = 73 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 15 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 6 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2 to 6 V
• Pin and function compatible with 74LS652
Note 1: Do not apply a signal to any bus terminal when it is in the output mode. Damage may result.
Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull
down resistors.
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2007-10-01