TC74HC646AP_07 Datasheet, PDF (1/8 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic Octal Bus Transceiver/Register (3-state)

TC74HC646AP
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC646AP
Octal Bus Transceiver/Register (3-state)
The TC74HC646A is high speed CMOS OCTAL BUS
TRANSCEIVER/REGISTERs fabricated with silicon gate C²MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
This device is bus transceiver with 3-state outputs, D-type
flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the internal registers.
When the direction input (DIR) is held high, the A1 thru A8
become inputs and the B1 thru B8 become outputs. When the
DIR input is held low, the A1 thru A8 become output and the B1
Weight: 1.50 g (typ.)
thru B8 become inputs.
The enable input G is held high, both the A Bus and B Bus become high impedance.
The select inputs (SAB, SBA) can muiltiplex stored and real-time (transparent mode) data.
Data on the A Bus or B Bus can be clocked into the registers on the positive going transition of either CAB or
CBA clock inputs, respectively.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features (Note 1) (Note 2)
• High speed: f_max = 73 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 15 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 6 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2 to 6 V
• Pin and function compatible with 74LS646
Note 1: Do not apply a signal to any bus terminal when it is in the out put mode. Damage may result.
Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull
down resistors.
Pin Assignment
1
2007-10-01