TC74HC4514AP_07 Datasheet, PDF (1/8 Pages) Toshiba Semiconductor – 4-to-16 Line Decoder/Latch

TC74HC4514AP
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC4514AP
4-to-16 Line Decoder/Latch
The TC74HC4514A are high speed CMOS 4-LINE TO 16-LINE
DECODER WITH LATCHED INPUTs fabricated with silicon
gate C²MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
The selected output is enabled by a low on the inhibit input
(INHIBIT). A binary code stored in the four input latches (A thru
D) is decided and provides a high level at the corresponding one
of sixteen outputs. When the INHIBIT is held low, all outputs are
kept low however, the latch function is available.
The data applied to the data inputs are transferred to the
Weight: 1.50 g (typ.)
outputs of latches when the strobe input is held high. When the
strobe input is taken low, the data is retained at the output of the latches.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features
• High speed: t_pd = 18 ns (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2 to 6 V
• Pin and function compatible with 4514B
Pin Assignment
1
2007-10-01