TC74HC4024AP_07 Datasheet, PDF (1/8 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic 7-Stage Binary Counter

TC74HC4024AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC4024AP,TC74HC4024AF
7-Stage Binary Counter
The TC74HC4024A is a high speed CMOS 7-STAGE BINARY
COUNTER fabricated with silicon gate C²MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
A negative transition on the CK input brings one increment
to the counter.
A CLR input is used to reset the counter to the all low level
state. A high level at CLR accomplishes the reset function.
All divided output stages are provided, and the last stage,
1/128 divided frequency will be obtained.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f_max = 70 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2~6 V
• Pin and function compatible with 4024B
Pin Assignment
TC74HC4024AP
TC74HC4024AF
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
: 0.96 g (typ.)
: 0.18 g (typ.)
1
2007-10-01