TC74HC40105AP Datasheet, PDF (1/11 Pages) Toshiba Semiconductor – 4 Bit × 16 Word FIFO Register

TC74HC40105AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC40105AP,TC74HC40105AF
4 Bit × 16 Word FIFO Register
The TC74HC40105A is a high speed CMOS 4 bit × 16 word
first-in, first-out (FIFO) Strage Register fabricated with silicon
gate C²MOS technology.
It achieves the high speed operation while maintaining the
CMOS low power dissipation.
The device is capable of handling 16 four-bit words and it is
possible to handle the input and output data at different shifting
rates.
When the DATA-IN-READY (DIR) is high, data is written into
the registers by a low to high transition of the SHIFT IN (SI)
input. And when DATA-OUT-READY (DOR) is high, data is read
out of the registers by a high to low transition of the SHIFT
OUT ( SO ) input.
If the MASTER RESET (MR) is high, the DIR goes high and
DOR goes low. The data in the internal registers are not changed
but are declared invalid.
The TC74HC40105A can be cascaded to form longer registers
or wider words.
The DATA OUTPUTs (Qn) are 3-State Outputs. When
OUTPUT ENABLE ( OE ) is held high, the Qn’s are in high
impedance state.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f_max 25 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 10 LSTTL loads for DIR, DOR
15 LSTTL loads for Q0 to Q3
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
for DIR, DOR
|I_OH| = I_OL = 6 mA (min)
for Q0 to Q3
• ^{Balanced propagation delays: t}pLH ^{∼− t}pHL
• Wide operating voltage range: V_CC (opr) = 2 to 6 V
TC74HC40105AP
TC74HC40105AF
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
: 1.00 g (typ.)
: 0.18 g (typ.)
1
2007-10-01