TC74HC40102AP_07 Datasheet, PDF (1/14 Pages) Toshiba Semiconductor – Dual BCD Programmable Down Counter

TC74HC40102,40103AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC40102AP,TC74HC40102AF
TC74HC40103AP,TC74HC40103AF
TC74HC40102AP/AF Dual BCD Programmable Down Counter
TC74HC40103AP/AF 8-Bit Binary Programmable Down Counter
The TC74HC40102A and TC74HC40103A are high speed
CMOS PROGRAMMABLE DOWN COUNTERS fabricated with
silicon gate C2MOS technology.
They achieve the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
The output terminal ( CO/ZD ) goes to an active low state when
the down count reaches zero. Since the TC74HC40102A is
designed as a BCD counter, programming up to 99 counts is
possible. The TC74HC40103A, with its 8-bit binary construction,
can be set to provide up to 255 counts.
Both devices have Inhibit Clock ( CI/CE ), Asynchronous Preset
Control ( APE ), Synchronous Preset ( SPE ) and Clear Control
( CLR ) inputs for setting the counter to the maximum counting
mode.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f_max 40 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2 to 6 V
• Pin and function compatible with 40102B, 40103B
Pin Assignment
TC74HC40102AP, TC74HC40103AP
TC74HC40102AF, TC74HC40103AF
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
: 1.00 g (typ.)
: 0.18 g (typ.)
1
2007-10-01