TC74HC390AP_07 Datasheet, PDF (1/11 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic Dual Decade Counter

TC74HC390AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC390AP,TC74HC390AF,TC74HC390AFN
Dual Decade Counter
The TC74HC390A is a high speed CMOS DUAL DECADE
COUNTER fabricated with silicon gate C²MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
It consists of two independent 4-bit counters, each composed of
a divide-by-two and a divide-by-five counter. The divide-by-two
counter is incremented on the negative going transition of clock A
( CKA ). The divided-by-five counter is incremented on the
negative going transition of clock B ( CKB ). The counter can be
cascaded to form decade, bi-quinary, or various combinations up
to a divide-by-100 counter. When the CLR input is set high, the
Q outputs are set to low independent of the clock inputs.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f_max = 84 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• ^{Balanced propagation delays: t}pLH ^{∼− t}pHL
• Wide operating voltage range: V_CC (opr) = 2~6 V
• Pin and function compatible with 74LS390
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC390AP
TC74HC390AF
TC74HC390AFN
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
1
2007-10-01