TC74HC279AP_07 Datasheet, PDF (1/8 Pages) Toshiba Semiconductor – Quad S-R Latch

TC74HC279AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC279AP,TC74HC279AF
Quad S -R Latch
The TC74HC279A is a high speed CMOS QUAD S-R LATCH
fabricated with silicon gate C²MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
Each latch has an independent Q output and Set and Reset
inputs. S and R are active low. When S input is low, the Q
output goes high and when R input is low, the Q output goes
low. When both S and R are low, S takes precedence
resulting Q = low. When both of S and R are held high, Q
output doesn’t change.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: t_pd = 12 ns (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 2 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2 to 6 V
• Pin and function compatible with 74LS279
Pin Assignment
TC74HC279AP
TC74HC279AF
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
: 1.00 g (typ.)
: 0.18 g (typ.)
1
2007-10-01