TC74HC166AP_07 Datasheet, PDF (1/11 Pages) Toshiba Semiconductor – 8-Bit Shift Register (P-IN, S-OUT)

TC74HC166AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC166AP,TC74HC166AF,TC74HC166AFN
8-Bit Shift Register (P-IN, S-OUT)
The TC74HC166A is a high speed CMOS 8-BIT
PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT REGISTER
fabricated with silicon gate C²MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
It consists of parallel-in or serial-in, serial-out 8-bit shift
register with a gated clock input and an overriding clear input.
The parallel-in or serial-in modes are controlled by the
SHIFT/ LOAD input. When the SHIFT/ LOAD input is held
high, the serial data input is enabled and the eight flip-flops
perform serial shifting on each clock pulse. When held low, the
parallel data inputs are enabled and synchronous loading occurs
on the next clock pulse. Clocking is accomplished on the
low-to-high transition of the clock pulse. The CK-INH input
should be shifted high only while the CK input is held high. A
direct clear input overrides all other inputs, includng the clock,
and sets all the flip-flops to zero. Functional details are shown in
the truth table and the timing charts.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f_max = 57 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive immunity: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2 to 6 V
• Pin and function compatible with 74LS166
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC166AP
TC74HC166AF
TC74HC166AFN
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
1
2007-10-01