TC74HC155AP_07 Datasheet, PDF (1/9 Pages) Toshiba Semiconductor – Dual 2-to-4 Line Decoder 3-to-8 Line Decoder

TC74HC155AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC155AP,TC74HC155AF,TC74HC155AFN
Dual 2-to-4 Line Decoder 3-to-8 Line Decoder
The TC74HC155A is a high speed CMOS DUAL 2-to-4 LINE
DECODER fabricated with silicon gate C²MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
It features dual 1-to-4 line demultiplexers with individual
strobe input (1G and 2G), individual data inputs (1C and 2C) and
common binary address inputs (A and B).
When both decoders are enabled by the strobes, the inverted
output of 1C data and non-inverted output of 2C data will be
brought to the selected output pins of each section.
A 1-to-8 line demultiplexer can be easily built up by providing
a data signal to both the 1C and 2C inputs; the output order will
be 1Y3 (MSB), 1Y2, 1Y1, 1Y0, 2Y3, 2Y2, 2Y1, 2Y0 (LSB).
This device can be used as a 2-to-4 line decoder or a 3-to-8 line
decoder when 1C is held high and 2C is held low.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: t_pd = 12 ns (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2 to 6 V
• Pin and function compatible with 74LS155
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC155AP
TC74HC155AF
TC74HC155AFN
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
1
2007-10-01