TC74HC125AP_07 Datasheet, PDF (1/9 Pages) Toshiba Semiconductor – Quad Bus Buffer

TC74HC125AP/AF/AFN,126AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC125AP,TC74HC125AF,TC74HC125AFN
TC74HC126AP,TC74HC126AF
TC74HC125AP/AF/AFN Quad Bus Buffer
TC74HC126AP/AF
Quad Bus Buffer
The TC74HC125A/126A are high speed CMOS QUAD BUS
BUFFERs fabricated with silicon gate C²MOS technology.
They achieve the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
The TC74HC125A requires the 3-state control input G to be
set high to place the output into the high impedance state,
whereas the TC74HC126A requires the control input to be set
low to place the output into high impedance.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: t_pd = 10 ns (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 15 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 6 mA (min)
• ^{Balanced propagation delays: t}pLH ^{∼− t}pHL
• Wide operating voltage range: V_CC (opr) = 2 to 6 V
• Pin and function compatible with 74LS125/126
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC125AP, TC74HC126AP
TC74HC125AF, TC74HC126AF
TC74HC125AFN
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
SOL14-P-150-1.27
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.12 g (typ.)
1
2007-10-01