TC74HC107AF_07 Datasheet, PDF (1/9 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Clear

TC74HC107AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC107AP,TC74HC107AF,TC74HC107AFN
Dual J-K Flip Flop with Clear
The TC74HC107A is a high speed CMOS DUAL J-K FLIP
FLOP fabricated with silicon gate C²MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
In accordance with the logic levels applied to the J and K
inputs, the outputs change state on the negative going transition
of the clock pulse.
CLR is independent of the clock and is accomplished by a low
logic level on the input.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f_max = 75 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 2 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2~6 V
• Pin and function compatible with 74LS107
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC107AP
TC74HC107AF
TC74HC107AFN
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
SOL14-P-150-1.27
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.12 g (typ.)
IEC Logic Symbol
1
2007-10-01