TC74AC74F_07 Datasheet, PDF (1/10 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop with Preset and Clear

TC74AC74P/F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC74P,TC74AC74F,TC74AC74FN,TC74AC74FT
Dual D-Type Flip Flop with Preset and Clear
The TC74AC74 is an advanced high speed CMOS D-FLIP
FLOP fabricated with silicon gate and double-layer metal wiring
C²MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The signal level applied to the D INPUT is transferred to Q
OUTPUT during the positive going transition of the CK pulse.
CLR and PR are independent of the CK and are
accomplished by setting the appropriate input to an “L” level.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f_max = 200 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Symmetrical output impedance: |I_OH| = I_OL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_{CC (opr)} = 2 V to 5.5 V
• Pin and function compatible with 74F74
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC74P
TC74AC74F
TC74AC74FN
TC74AC74FT
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
SOL14-P-150-1.27
TSSOP14-P-0044-0.65A
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.12 g (typ.)
: 0.06 g (typ.)
1
2007-10-01