TC74AC175F_07 Datasheet, PDF (1/10 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic Quad D-Type Flip Flop with Clear

TC74AC175P/F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC175P,TC74AC175F,TC74AC175FN,TC74AC175FT
Quad D-Type Flip Flop with Clear
The TC74AC175 is an advanced high speed CMOS QUAD
D-TYPE FLIP FLOP fabricated with silicon gate and
double-layer metal wiring C²MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
These four flip-flops are controlled by a clock input (CK) and a
clear input ( CLR ).
The information data applied to the D inputs (D1 thru D4) are
transferred to the outputs (Q1 thru Q4 and Q1 thru Q4 ) on the
positive-going edge of the clock pulse.
Reset function is accomplished when the clear input is taken
low, and all Q outputs are kept in low level regardless of other
input conditions.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f_max = 170 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 8 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Symmetrical output impedance: |I_OH| = I_OL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_{CC (opr)} = 2 to 5.5 V
• Pin and function compatible with 74F175
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC175P
TC74AC175F
TC74AC175FN
TC74AC175FT
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
: 0.06 g (typ.)
1
2007-10-01