TC74AC139P_07 Datasheet, PDF (1/9 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic Dual 2-to-4 Line Decoder

TC74AC139P/F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC139P,TC74AC139F,TC74AC139FN,TC74AC139FT
Dual 2-to-4 Line Decoder
The TC74AC139 is an advanced high speed CMOS 2-to-4 LINE
DECODER fabricated with silicon gate and double-layer metal
wiring C²MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The active low enable input can be used for gating or it can be
used as a data input for demultiplexing applications.
When the enable input is held “H”, all four outputs are fixed at
a high logic level independent of the other inputs.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: t_pd = 5.9 ns (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 8 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Symmetrical output impedance:
|I_OH| = I_OL = 24 mA (min) Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2 V to 5.5 V
• Pin and function compatible with 74F139
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC139P
TC74AC139F
TC74AC139FN
1G 1
1A 2
1B ³
1Y0 4
1Y1 5
1Y2 6
1Y3 7
GND 8
(top view)
16 V_CC
15 2G
14 2A
13 2B
12 2Y0
11 2Y1
10 2Y2
9 2Y3
TC74AC139FT
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
: 0.06 g (typ.)
1
2007-10-01