TC74AC112P_07 Datasheet, PDF (1/9 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Preset and Clear

TC74AC112P/F/FN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC112P,TC74AC112F,TC74AC112FN
Dual J-K Flip Flop with Preset and Clear
The TC74AC112 is an advanced high speed CMOS DUAL J-K
FLIP FLOP fabricated with silicon gate and double-layer metal
wiring C²MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
In accordance with the logic level given J and K input this
device changes state on negative going transition of the clock
pulse. CLEAR and PRESET are independent of the clock and
accomplished by a low logic level on the corresponding input.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f_max = 170 MHz (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Symmetrical output impedance: |I_OH| = I_OL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2 to 5.5 V
• Pin and function compatible with 74F112
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC112P
TC74AC112F
TC74AC112FN
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
1
2007-10-01