TC58NVG0S3AFT05 Datasheet, PDF (1/33 Pages) Toshiba Semiconductor – 1 GBIT (128M × 8 BITS) CMOS NAND EEPROM

TC58NVG0S3AFT05
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1 GBIT (128M × 8 BITS) CMOS NAND EEPROM
DESCRIPTION
The TC58NVG0S3A is a single 3.3-V 1G-bit (1,107,296,256 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND EEPROM) organized as (2048 + 64) bytes × 64 pages × 1024 blocks. The device has a
2112-byte static registers which allow program and read data to be transferred between the register and the
memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes
+ 4 Kbytes: 2112 bytes × 64 pages).
The TC58NVG0S3A is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed
making the device most suitable for applications such as solid-state file storage, voice recording, image file
memory for still cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell array 2112 × 64K × 8
Register
2112 × 8
Page size
2112 bytes
Block size
(128K + 4K) bytes
• Modes
Read, Reset, Auto Page Program
Auto Block Erase, Status Read
• Mode control
Serial input/output
Command control
• Powersupply
VCC = 2.7 V to 3.6 V
• Program/Erase Cycles 1E5 Cycles (With ECC)
• Access time
Cell array to register 25 µs max
Serial Read Cycle
50 ns min
• Operating current
Read (50 ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
50 µA max
• Package
TSOPI48-P-1220-0.50 (Weight: 0.53 g typ.)
PIN ASSIGNMENT (TOP VIEW)
NC 1
NC 2
NC 3
NC 4
NC 5
GND 6
RY / BY 7
RE 8
CE 9
NC 10
NC 11
VCC 12
VSS 13
NC 14
NC 15
CLE 16
ALE 17
WE 18
WP 19
NC 20
NC 21
NC 22
NC 23
NC 24
PIN NAMES
48 NC
47 NC
46 NC
45 NC
44 I/O8
43 I/O7
42 I/O6
41 I/O5
40 NC
39 NC
38 NC
37 VCC
36 VSS
35 NC
34 NC
33 NC
32 I/O4
31 I/O3
30 I/O2
29 I/O1
28 NC
27 NC
26 NC
25 NC
I/O1 to I/O8
CE
WE
RE
CLE
ALE
WP
RY / BY
GND
V_CC
V_SS
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Ground Input
Power supply
Ground
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