TC55NEM208AFPV Datasheet, PDF (1/11 Pages) Toshiba Semiconductor – 524,288-WORD BY 8-BIT STATIC RAM

TC55NEM208AFPV/AFTV55,70
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55NEM208AFPV/AFTV is a 4,194,304-bit static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a
single 2.7 to 5.5 V power supply. Advanced circuit technology provides both high speed and low power at an
operating current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power
mode at 1 µA standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is
used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This
device is well suited to various microprocessor system applications where high speed, low power and battery
backup are required. And, with a guaranteed operating range of −40° to 85°C, the TC55NEM208AFPV/AFTV can
be used in environments exhibiting extreme temperature conditions. The TC55NEM208AFPV/AFTV is available in
a standard plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin
thin-small-outline package (TSOP).
FEATURES
• Low-power dissipation
Operating: 15 mW/MHz (typical)
• Single power supply voltage of 2.7 to 5.5 V
• Power down features using CE .
• Data retention supply voltage of 2.0 to 5.5 V
• Direct TTL compatibility for all inputs and outputs
• Wide operating temperature range of −40° to 85°C
• Standby Current (maximum):20 µA
• Access Times (maximum):
TC55NEM208AFPV/AFTV
55
70
Access Time
55 ns
70 ns
CE Access Time
55 ns
70 ns
OE Access Time
30 ns
35 ns
• Package:
SOP32-P-525-1.27 (AFPV) (Weight:
TSOP II32-P-400-1.27 (AFTV) (Weight:
g typ)
g typ)
PIN ASSIGNMENT (TOP VIEW)
32 PIN SOP & TSOP
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O1 13
I/O2 14
I/O3 15
GND 16
32 VDD
31 A15
30 A17
29 R/W
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
(AFPV/AFTV)
PIN NAMES
A0~A18
R/W
OE
CE
I/O1~I/O8
V_DD
GND
Address Inputs
Read/Write Control
Output Enable
Chip Enable
Data Inputs/Outputs
Power
Ground
2002-10-31 1/11