T3GF3WBG Datasheet, PDF (1/13 Pages) Toshiba Semiconductor – Dual-Supply Bus Transceiver for SD Memory Card

CMOS Digital Integrated Circuits Silicon Monolithic
T3GF3WBG
T3GF3WBG
1. Functional Description
• Dual-Supply Bus Transceiver for SD Memory Card
2. General
This device is an advanced high-speed dual-supply bus transceiver fabricated with silicon-gate CMOS technology.
Designed for use as an interface between a 1.8-V bus and a 1.8-V/2.9-V bus in mixed 1.8-V/2.9-V supply systems.
The A-port interfaces with the 1.8-V bus, the B-port with the 1.8-V/2.9-V bus.
The direction of data transmission is determined by the level of the DIR input.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
3. Features
(1) Compliant with SD specification Part 1 Physical Layer Specification 3.0 (SDR12/SDR25/DDR50)
(2) Bidirectional interface between 1.8-V and 2.9-V buses
(3) High-speed operation: t_pd (A to B) = 5.0 ns (max) (V_CCA = 1.8 ± 0.15 V, V_CCB = 2.9 ± 0.1 V)
t_pd (B to A) = 5.0 ns (max) (V_CCA = 1.8 ± 0.15 V, V_CCB = 2.9 ± 0.1 V)
t_pd (A to B) = 7.0 ns (max) (V_CCA = 1.8 ± 0.15 V, V_CCB = 1.8 ± 0.1 V)
t_pd (B to A) = 7.0 ns (max) (V_CCA = 1.8 ± 0.15 V, V_CCB = 1.8 ± 0.1 V)
(4) Output current: I_OHB/I_OLB = ±6 mA (min) (V_CCB = 2.8 V)
I_OHA/I_OLA = ±6 mA (min) (V_CCA = 1.65 V)
(5) Integrated EMI filter on B-port
(6) Integrated pull-up and pull-down resistors on B-port
(7) Latch-up performance: ±200 mA
(8) ESD performance: Human body model > ±2000 V
IEC61000-4-2 Level 4 (Contact) > ±8 kV (SD card side)
IEC61000-4-2 Level 4 (Air) > ±15 kV (SD card side)
CDM > 500 V
(9) Ultra-small package: WCSP25
1
2012-07-26
Rev.1.0