SSM6N25TU Datasheet, PDF (1/7 Pages) Toshiba Semiconductor – High Speed Switching Applications

SSM6N25TU
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type (U-MOSIII)
SSM6N25TU
High Speed Switching Applications
• Optimum for high-density mounting in small packages
• Low on-resistance: R_on = 395mΩ (max) (@V_GS = 1.8 V)
R_on = 190mΩ (max) (@V_GS = 2.5 V)
R_on = 145mΩ (max) (@V_GS = 4.0 V)
Absolute Maximum Ratings (Ta = 25°C)
(Q1, Q2 Common)
Characteristics
Symbol
Rating
Unit
Unit: mm
2.1±0.1
1.7±0.1
1
6
2
5
3
4
Drain-Source voltage
V_DS
20
V
Gate-Source voltage
V_GSS
± 12
V
Drain current
DC
Pulse
Drain power dissipation
I_D
0.5
A
I_DP
1.5
P_D
500
mW
(Note 1)
1.Source1
2.Gate1
3.Drain2
4.Source2
5.Gate2
6.Drain1
Channel temperature
T_ch
150
°C
Storage temperature range
T_stg
−55~150
°C
UF6
Note:
Using continuously under heavy loads (e.g. the application of
JEDEC
―
high temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
JEITA
TOSHIBA
―
2-2T1B
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Weight: 7.0 mg (typ.)
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and
individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1: Mounted on FR4 board. (total dissipation)
(25.4 mm × 25.4 mm × 1.6 t, Cu Pad: 645 mm² )
Marking
654
Equivalent Circuit (top view)
6 54
NH
Q1
Q2
123
123
Handling Precaution
When handling individual devices (which are not yet mounted on a circuit board), be sure that the environment is
protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects
that come into direct contact with devices should be made of anti-static materials.
1
2007-11-01