SSM4K27CT Datasheet, PDF (1/5 Pages) Toshiba Semiconductor – Switching Applications

SSM4K27CT
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type (U-MOSⅢ)
SSM4K27CT
○ Switching Applications
• Suitable for high-density mounting due to compact package
• Low on-resistance:
R_on = 205 mΩ (max) (@V_GS = 4.0 V)
R_on = 260 mΩ (max) (@V_GS = 2.5 V)
R_on = 390 mΩ (max) (@V_GS = 1.8 V)
Absolute Maximum Ratings (Ta = 25°C)
Top view
0.05±0.04
0.8±0.05
0.5
Unit: mm
0.2±0.02
Characteristics
Symbol
Rating
Unit
Drain-Source voltage
V_DS
20
V
Gate-Source voltage
V_GSS
±12
V
Drain current
DC
I_D
Pulse
I_DP
0.5
A
1.0
Drain power dissipation
P_D (Note 1)
400
mW
Channel temperature
T_ch
150
°C
Storage temperature range
T_stg
−55~150
°C
Side view
1 :Gate 2:Source
CST4 ^3,4:Drain
Note:
Using continuously under heavy loads (e.g. the application of
JEDEC
⎯
high temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
JEITA
TOSHIBA
⎯
2-1M1A
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Weight: 1.1 mg (typ.)
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and
individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1: Mounted on FR4 board.
(25.4 mm × 25.4 mm × 1.6 t, Cu Pad: 645 mm² )
Marking (top view) Electrode Layout (bottom view) Equivalent Circuit (top view)
4
3
4
3
3
4
1
2
2
1
1
2
Polarity marking
Handling Precaution
1 Gate
2 Source
3 Drain
4 Drain
When handling individual devices (which are not yet mounted on a circuit board), ensure that the environment is
protected against static electricity. Operators should wear anti-static clothing, and containers and other objects that come
into direct contact with devices should be made of anti-static materials.
1
2007-11-01