SSM3J15FV Datasheet, PDF (1/5 Pages) Toshiba Semiconductor – Field Effect Transistor Silicon P Channel MOS Type High Speed Switching Applications Analog Switch Applications

SSM3J15FV
TOSHIBA Field Effect Transistor Silicon P Channel MOS Type
SSM3J15FV
High Speed Switching Applications
Analog Switch Applications
• Optimum for high-density mounting in small packages
• Low on-resistance : R_on = 12 Ω (max) (@V_GS = −4 V)
: R_on = 32 Ω (max) (@V_GS = −2.5 V)
Absolute Maximum Ratings (Ta = 25°C)
Unit: mm
1.2 ± 0.05
0.80 ± 0.05
Characteristics
Symbol
Rating
Unit
Drain-Source voltage
V_DS
−30
V
Gate-Source voltage
V_GSS
±20
V
Drain current
DC
Pulse
I_D
−100
mA
I_DP
−200
Drain power dissipation (Ta = 25°C) P_D (Note 1)
150
mW
Channel temperature
T_ch
150
°C
Storage temperature range
T_stg
−55~150
°C
Note: Using continuously under heavy loads (e.g. the application of
high temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling
Precautions”/“Derating Concept and Methods”) and individual
reliability data (i.e. reliability test report and estimated failure rate,
etc).
Note 1: Total rating, mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 t, Cu Pad: 0.585 mm²)
1
1
3
2
VESM
1.GATE
2.SOURCE
3.DRAIN
JEDEC
JEITA
TOSHIBA
―
―
2-1L1B
Weight: 0.0015 g(typ.)
0.5mm
0.45mm
0.45mm
0.4mm
Marking
3
Equivalent Circuit (top view)
3
DQ
1
2
1
2
Handling Precaution
When handling individual devices (which are not yet mounted on a circuit board), be sure that the environment is
protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects
that come into direct contact with devices should be made of anti-static materials.
1
2007-11-01