XC25BS5_002 Datasheet, PDF (5/10 Pages) Torex Semiconductor – PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits(For Low Frequency Range)

■TYPICAL APPLICATION CIRCUITS
① Q1 Pin - reference oscillation, reference oscillation/2, comparative frequency
XC25BS5
Series
② Q1 Pin - GND
■NOTE
(1) Please insert a by-pass capacitor of 0.1μF.
(2) Rq0 and Rq1 are matching resistors. Their use is recommended in order to counter unwanted radiations.
(3) Please place a by-pass capacitor and matching resistors as close to the IC as possible. It may be that the
output cannot be locked if the by-pass capacitor is not close enough to the IC. Further, there is a possibility of
unwanted radiation occurrence between the resistor and the IC pin if the matching resistor is not close enough to
the IC.
(4) When selecting GND for the Q1 pin, although the output of Q1 pin is GND level, it is also recommended that the
Q1 pin be connected to GND pattern on the PCB.
(5) When the CE pin is not controlled by external signals, it is recommended that a time constant circuit of R1=1kΩ
×C1 = 0.1μF be added for stability.
(6) With this IC, output is achieved by dividing and multiplying the reference oscillation by means of the PLL circuit.
In cases where this output is further used as a reference oscillation of another PLL circuit, it may be that the final
output signal's jitter increases, so all necessary precautions should be taken to avoid this.
(7) It is recommended that a low noise power supply, such as a series regulator, be used for the supply voltage.
Using a power supply such as a switching regulator might lead to a larger jitter, which in turn may lead to an
inability to lock due to the ripple of the switching regulator.
(8) As for this IC, synchronization of input and output signal’s edge is not guaranteed though the input frequency
operates to the output frequency multiply.
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