XC6108 Datasheet, PDF (13/18 Pages) Torex Semiconductor – Voltage Detector with Separated Sense Pin and Delay Type Capacitor

XC6108
Series
■OPERATIONAL EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on the next page.
① As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged
to the power supply input voltage, (VIN: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (VSEN) starts dropping to
reach the detect voltage (VDF) (VSEN>VDF), the output voltage (VOUT) keeps the “High” level (=VIN).
* If a pull-up resistor of the XC6108N series (N-ch open drain) is connected to added power supply different from the input
voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected.
② When the sense pin voltage keeps dropping and becomes equal to the detect voltage, an N-ch transistor for the delay
capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit, which uses
the delay capacitance pin as power input, the reference voltage operates as a comparator of VIN, and the output voltage
changes into the “Low” level (=VSS). The detect delay time [TDF] is defined as time which ranges from VSEN=VDF to the
VOUT of “Low” level (especially, when the Cd pin is not connected: TDF0).
③ While the sense pin voltage keeps below the detect voltage, the delay capacitance is discharged to the ground voltage
(=VSS) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to reach the
release voltage (VSEN< VDF +VHYS).
④ When the sense pin voltage continues to increase up to the release voltage level (VDF+VHYS), the N-ch transistor for the
delay capacitance discharge will be turned OFF, and the delay capacitance will start discharging via a delay resistor
(Rdelay). The internal circuit, which uses the delay capacitance pin as power input, will operate as a hysteresis
comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic Threshold: VTHL=VSS) while the sense pin voltage keeps
higher than the detect voltage (VSEN > VDF).
⑤ While the delay capacitance pin voltage (VCD) rises to reach the delay capacitance pin threshold voltage (VTCD) with the
sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC
series circuit. Assuming the time to the release delay time (TDR), it can be given by the formula (1).
TDR = －Rdelay×Cd×In (1－VTCD / VIN) …(1)
* In = a natural logarithm
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin voltage is VIN /2 (TYP.)
TDR = 2.0e6×Cd×0.69…(2)
As an example, presuming that the delay capacitance is 0.68μF, TDR is :
2.0e6×0.68e－6×0.69 = 938 (ms)
* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground
(=VSS) level because time described in ③ is short.
⑥ When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (VCD=VTCD), output of an
internal circuit, which uses the delay capacitance pin as power input will be inverted. As a result, the output voltage
changes into the “High” (=VIN) level. TDR0 is defined as time which ranges from VSEN=VDF+VHYS to the VOUT of “High”
level without connecting to the Cd.
⑦ While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitance pin is charged until the
delay capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=VIN)
level.
●Release Delay Time Chart
Delay Capacitance [Cd]
(μF)
0.010
0.022
0.047
0.100
0.220
0.470
1.000
Release Delay Time [TDR]
(TYP.)
(ms)
13.8
30.4
64.9
138
304
649
1380
Release Delay Time [TDR]
(MIN. ~ MAX.)
(ms)
11.0 ~ 16.6
24.3 ~ 36.4
51.9 ~ 77.8
110 ~ 166
243~ 364
519 ~ 778
1100 ~ 1660
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