TTP259 Datasheet, PDF (42/81 Pages) Tontek Design Technology – Preliminary

Preliminary
TTP259
TonTouch^TM
Set IICCON1<0> (IICEN) can enable all IIC block, IICCON0<0> (IICMOD)
can select IIC operation in normal mode or fast read mode. The first byte of
data transfer immediately following the START signal is the slave address
transmitted by the master. This is a seven bit long calling address followed by
a R/W bit in Normal mode. Fast read mode only have transmit mode, so R/W
bit must be 1.
When START signal is detected, IICSTS<2> (MBB) is set. When STOP
signal is detected, MBB is cleared. IICSTS<3> (MAASF) is set, when IIC
device match the calling address. When MAASF is set, and INTF1<2> (IICF)
is also set. An interrupt is generated if the INTC1<2> (IICIE) be set. User can
check IICSTS<1> (SRWB) to know IIC device operate in transmit or receive
mode. When IICF is set, an interrupt is generated to the CPU. IICF is set when
one of the following event occurs:
1) IIC device address match in normal mode.
2) Completion of one byte of data transfer. It is set at the falling edge of
the 9th clock in normal mode.
3) Completion of IICRDAT(L/H)0 data transfer and IICRDAT(L/H)1 load
on IICDAT(L/H) in fast read mode.
When IIC device operate in transmit mode, master’s acknowledge store in
IICSTS<0> (TXACK). If detect acknowledge, this bit set, if not, this bit clear.
IICDAT(L/H) only use in normal mode. In transmit mode, data written into
the register to send to the bus automatically, with the most significant bit out
first. In receive mode, reading of this register initiates receiving of the next
byte data. IICRDAT(L/H)0 and IICRDAT(L/H)1 only use in fast mode. IIC
device transmit IICRDAT(L/H)0 first, completion of transfer, IICRDAT(L/H)1
continue transmit to bus automatically.
Whenever IICRDAT(L/H)0 transfer is complete, IICRDAT(L/H)1 will
automatically load transfer buffer, and generates an interrupt flag notify
updatable. If the data transfer will be more than two bytes, you can create a
data counter, interrupt flag is generated every time, data will be placed in
IICRDAT(L/H)0 and IICRDAT(L/H)1 by order by software, however, if the
master halfway want to re-read the beginning of the data, when the data
counter is not starting from scratch, data can not be read correctly, this
situation can be set STIE be 1, when receiving the START signal from IIC BUS,
an interrupt is generated, by receiving this start signal, the data counter is reset
by the software, so you can re-read the data correctly. STIF can only be actived
in fast read mode.
2015/05/25
Page 42 of 81
Ver: 1.1