T35L6432B Datasheet, PDF (12/16 Pages) Taiwan Memory Technology – 64K x 32 SRAM

tm TE
CH
READ TIMING
CLK
ADSP
t_{K C}
t_{A D SS}
t_{K H}
t_{A D SH} ^{tK L}
ADSC
A D D R ESS
G W ,B W E
B W 1-B W 4
CE
(N O T E 2)
ADV
t_{A D SS} t_{A D SH}
t_{A S} t_{A H}
A1
A2
t_{W S} t_{W H}
t_CES t_CEH
t_{A A S}
t_{A A H}
OE
Q
t_{O EZ}
t_{K Q LZ}
t_{K Q}
t_{O EH Z}
Q (A 1)
t_{O ELZ}
t_{K Q}
t_{K Q X}
Q (A 2)
Q (A 2+ 1)
Single R E A D
T35L6432B
D eselect C ycle
(N o te4 )
A D V suspends burst
Q (A 2+ 2 )
Q (A 2+ 3)
BURST READ
t_{K Q H Z}
Q (A 2)
Q (A 2+ 1)
Q (A 2+ 2)
B u rst w raps aro un d to
its in ital state
:D o n 't c are
:U N D E F IN E D
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW
and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
OE does not cause Q to be driven until after the following clock rising edge.
4. Output are disabled ^tKQHZ after diselect.
Taiwan Memory Technology, Inc. reserves the right P. 12
to change products or specifications without notice.
Publication Date: JUL. 2002
Revision: A