T4312816B Datasheet, PDF (1/70 Pages) Taiwan Memory Technology – 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM

tm TE
CH
SDRAM
T4312816B
8M x 16 SDRAM
2M x 16bit x 4Banks Synchronous DRAM
FEATURES
• ^{Fast access time from clock: 5/5.4 ns}
• ^{Fast clock rate: 166/143 MHz}
• ^{Fully synchronous operation}
• ^{Internal pipelined architecture}
• ^{2M word x 16-bit x 4-bank}
• ^{Programmable Mode registers}
- CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
• ^{Auto Refresh and Self Refresh}
• ^{4096 refresh cycles/64ms}
• ^{CKE power down mode}
• ^{Single +3.3V power supply}
• ^{Interface: LVTTL}
• ^{54-pin 400 mil plastic TSOP II package}
• ^{Lead-free package is available}
ORDERING INFORMATION
Key Specifications
T4312816B
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK(max.)
tRAS Row Active time(min.)
tRC Row Cycle time(min.)
- 6/7
6/7 ns
5/5.4 ns
42/42 ns
60/63 ns
Ordering Information
Part Number
Frequency
T4312816B –6S
166MHz
T4312816B –6SG
166MHz
T4312816B –7S
143MHz
T4312816B –7SG
“G” indicates Lead-free
143MHz
Package
TSOP II
TSOP II
TSOP II
TSOP II
GRNERAL DESCRIPTION
The T4312816B SDRAM is a high-speed CMOS
synchronous DRAM containing 128 Mbits. It is internally
configured as 4 Banks of 2M word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number
of locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which is
then followed by a Read or Write command.
The T4312816B provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the system
can choose the most suitable modes to maximize its
performance. These devices are well suited for applications
requiring high memory bandwidth and particularly well
suited to high performance PC applications.
PIN ARRANGEMENT (Top View)
VDD
1
DQ0
2
V DDQ
3
DQ1
4
DQ2
5
VSSQ
6
DQ3
7
DQ4
8
V DDQ
9
DQ5
10
DQ6
11
VSSQ
12
DQ7
13
VDD
14
DQML
15
/WE
16
/CA S
17
/RA S
18
/CS
19
BA0
20
BA1
21
A 1 0 (A P)
22
A0
23
A1
24
A2
25
A3
26
VDD
27
54
VSS
53
DQ15
52
VSSQ
51
DQ14
50
DQ13
49
V DDQ
48
DQ12
47
DQ11
46
VSSQ
45
DQ10
44
DQ9
43
V DDQ
42
DQ8
41
VSS
40
NC
39
DQMU
38
CLK
37
CK E
36
NC
35
A11
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
28
VSS
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A