T4312816A Datasheet, PDF (1/29 Pages) Taiwan Memory Technology – 8M x 16 SDRAM

tm TE
CH
SDRAM
Preliminary T4312816A
8M x 16 SDRAM
2M x 16bit x 4Banks Synchronous DRAM
FEATURES
• 3.3V power supply
• Four banks operation
• LVTTL compatible with multiplexed address
• All inputs are sampled at the positive going
edge of system clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto refresh and self refresh
• 64ms refresh period (4K cycle)
• MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
• Available package type in 54 pin TSOP(II)
• Operating temperature : 0 ~ +70 °C
ORDERING INFORMATION
PART NO.
T4312816A-6S
MAX
TEMPERATURE
FREQUENCY
166 MHz
0 ~ +70°C
T4312816A-7S 143 MHz
0 ~ +70°C
T4312816A-7.5S 133 MHz
0 ~ +70°C
T4312816A-8S 125 MHz
0 ~ +70°C
T4312816A-10S 100 MHz
0 ~ +70°C
GRNERAL DESCRIPTION
The T4312816A is 134,217,728 bits
synchronous high data rate Dynamic RAM
organized as 4 x 2,097,152 words by 16 bits,
fabricated with high performance CMOS
technology .
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clockcycle . Range of operating
frequencies , programmable burst length and
programmable latencies allow the same device to
be useful for a variety of high bandwidth , high
performance memory system applications.
PIN ARRANGEMENT (Top View)
V DD
1
54
DQ0
2
53
V DDQ
3
52
DQ1
4
51
DQ2
5
50
V SSQ
6
49
DQ3
7
48
DQ4
8
47
V DDQ
DQ5
DQ6
9
46
5 4 P IN T S O P (II)
10
45
(4 0 0 m il x 8 7 5 m il)
11
(0 .8 m m P IN P IT C H )
44
V SSQ
12
43
DQ7
13
42
V DD
14
41
LD QM
15
40
WE
16
39
CAS
17
38
RAS
18
37
CS
19
36
BA0
20
35
BA1
21
34
A 1 0 /A P
22
33
A0
23
32
A1
24
31
A2
25
30
A3
26
29
V DD
27
28
V ss
DQ 15
V SSQ
DQ 14
DQ 13
V DDQ
DQ 12
DQ 11
V SSQ
DQ1
0
DQ9
V DDQ
DQ8
V ss
N .C /R F U
UDQM
CLK
CKE
N .C
A 11
A9
A8
A7
A6
A5
A4
V ss
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: APR. 2003
Revision: 0.B