T35L6464A Datasheet, PDF (1/16 Pages) Taiwan Memory Technology – 64K x 64 SRAM

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T35L6464A
SYNCHRONOUS
BURST SRAM
64K x 64 SRAM
3.3V SUPPLY, FULLY REGISTERED AND OUTPUTS,
BURST COUNTER
FEATURES
• Fast Access times: 5, 6, 7, and 8ns
• Fast clock speed: 100, 83, 66, and 50 MHz
• Provide high performance 3-1-1-1 access rate
• Fast OE access times: 5 and 6ns
• Single 3.3V +10% / -5V power supply
• Common data inputs and data outputs
• BYTE WRITE ENABLE and GLOBAL
WRITE control
• Five chip enables for depth expansion and
address pipelining
• Address, control, input, and output pipelined
registers
• Internally self -timed WRITE cycle
• WRITE pass-through capability
• Burst control pins ( interleaved or linear burst
sequence)
• High density, high speed packages
• Low capacitive bus loading
• High 30pF output drive capability at rated access
time
• SNOOZE MODE for reduced power standby
• Single cycle disable ( Pentium^{T M} BSRAM
compatible )
PIN ASSIGNMENT (Top View)
128127126125124123122121120119118117116115114113112111110109108107106105104103
VSSQ
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
VCCQ
VSSQ
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
VCCQ
VSSQ
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
VCCQ
1
102
2
101
3
100
4
99
5
98
6
97
7
96
8
95
9
94
10
93
11
92
12
91
13
90
14
89
15
88
16
87
17
128-pin QFP
86
18
19
or
85
84
20
128-pin LQFP
83
21
82
22
81
23
80
24
79
25
78
26
77
27
76
28
75
29
74
30
73
31
72
32
71
33
70
34
69
35
68
36
67
37
66
38
65
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VCCQ
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
VSSQ
VCCQ
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
VSSQ
VCCQ
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
VSSQ
OPTIONS
TIMING
5ns access/10ns cycle
6ns access/12ns cycle
7ns access/15ns cycle
8ns access/20ns cycle
MARKING
-5
-6
-7
-8
Package
128-pin QFP
Q
128-pin LQFP
L
Part Number Examples
PART NO.
T35L6464A -5Q
T35L6464A -5L
Pkg. BURST SEQUENCE
Q Interleaved
(MODE=NC or VCC)
L Linear (MODE=GND)
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS design using advanced triple-layer
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
The T35L6464A SRAM integrates 65536 x 64
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, three active LOW
chip enable (CE , CE2 and CE3 ), two additional
chip enables (CE2 and CE3) , burst control inputs
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: AUG. 1998
Revision: E