T35L6432A Datasheet, PDF (1/15 Pages) Taiwan Memory Technology – 64K x 32 SRAM

tm TE
CH
SYNCHRONOUS
BURST SRAM
T35L6432A
64K x 32 SRAM
3.3V supply, fully registered inputs and
outputs, burst counter
FEATURES
¡EFast Access times: 4.5, 5, 6, 7, and 8ns
¡EFast clock speed: 125,100, 83, 66, and 50 MHz
¡EProvide high performance 3-1-1-1 access rate
¡EFast OE access times: 4.5, 5 and 6ns
¡ESingle 3.3V +10%/-5% power supply
¡ECommon data inputs and data outputs
¡EBYTE WRITE ENABLE and GLOBAL WRITE
control
¡EThree chip enables for depth expansion and
address pipelining
¡EAddress, control, input, and output pipelined
registers
¡EInternally self-timed WRITE CYCLE
¡EWRITE pass-through capability
¡EBurst control pins ( interleaved or linear burst
sequence)
¡EHigh density, high speed packages
¡ELow capacitive bus loading
¡EHigh 30pF output drive capability at rated access
time
¡ESNOOZE MODE for reduced power standby
¡ESingle cycle disable ( Pentium^TM BSRAM
compatible )
PIN ASSIGNMENT (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQ17
DQ18
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VCCQ
DQ23
DQ24
NC
VCC
NC
VSS
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VCCQ
DQ31
DQ32
NC
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
100-pin QFP
68
14
67
15
or
66
16
17
100-pin TQFP
65
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQ16
DQ15
VCCQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VCCQ
DQ10
DQ9
VSS
NC
VCC
ZZ
DQ8
DQ7
VCCQ
VSSQ
DQ6
DQ5
DQ4
DQ3
VSSQ
VCCQ
DQ2
DQ1
NC
OPTIONS
TIMING
4.5ns access/8ns cycle
5ns access/10ns cycle
6ns access/12ns cycle
7ns access/15ns cycle
8ns access/20ns cycle
Package
100-pin QFP
100-pin TQFP
MARKING
-4.5
-5
-6
-7
-8
Q
T
Part Number Examples
PART NO. Pkg.
T35L6432A-5Q Q
T35L6432A-5T T
BURST SEQUENCE
Interleaved
(MODE=NC or VCC)
Linear (MODE=GND)
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS design using advanced triple-layer
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
The T35L6432A SRAM integrates 65536 x 32
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, address-pipelining
P. 1
Publication Date: DEC. 1998
Revision: A