T35L3232B Datasheet, PDF (1/19 Pages) Taiwan Memory Technology – 32K x 32 SRAM

tm TE
CH
SYNCHRONOUS
BURST SRAM
Preliminary T35L3232B
32K x 32 SRAM
Pipeline and Flow-Through Burst Mode
FEATURES
¡E FT pin for user configurable pipeline or
flow-through operation.
¡E Fast Access times:
- Pipeline – 3.8 / 4 / 4.5 ns
- Flow-through – 9 / 10 / 11ns
¡ESingle 3.3V +0.3V/-0.165V power supply
¡ECommon data inputs and data outputs
¡EIndividual BYTE WRITE ENABLE and
GLOBAL WRITE control
¡E Three chip enables for depth expansion and
address pipelining
¡E Clock-controlled and registered address, data
I/Os and control signals
¡EInternally self-timed WRITE CYCLE
¡EBurst control pins ( interleaved or linear burst
sequence)
¡EHigh 30pF output drive capability at rated
access time
¡ESNOOZE MODE for reduced power standby
¡E Burst Sequence :
- Interleaved (MODE=NC or VCC)
- Linear (MODE=GND)
OPTIONS
MARKING
-3.8
-4
Pipeline
3-1-1-1
Access
time
Cycle
time
Flow-
through
2-1-1-1
Access
time
Cycle
time
3.8ns
6.6ns
9ns
10.5ns
4ns
7.5ns
10ns
15ns
Package
100-pin QFP
Q
100-pin TQFP
T
Part Number Examples
PART NO.
Pkg.
T35L3232B-3.8Q
Q
T35L3232B-4T
T
-4.5
4.5ns
8.5ns
11ns
15ns
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs high-speed, low power
CMOS design using advanced triple-layer polysilicon,
double-layer metal technology. Each memory cell
consists of four transistors and two high valued resistors.
The T35L3232B SRAM integrates 32,768 x 32
bits SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst operation.
All synchronous inputs are gated by registers controlled
by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable ( CE ), depth-
expansion chip enables (CE2 and CE2), burst control
inputs (ADSC , ADSP, and ADV ), write enables
( BW1, BW2 , BW3 , BW4 , and BWE ), and
global write (GW ).
Asynchronous inputs include the output enable
( OE ), Snooze enable (ZZ) and burst mode control
(MODE). The data outputs (Q), enabled by OE , are
also asynchronous.
Addresses and chip enables are registered with
either address status processor ( ADSP ) or address
status controller (ADSC ) input pins. Subsequent burst
addresses can be internally generated as controlled by
the burst advance pin (ADV ).
Address and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles
can be one to four bytes wide as controlled by the write
control inputs. Individual byte write
allows individual byte to be written. BW1 controls
DQ1-DQ8. BW2 controls DQ9-DQ16. BW3
controls DQ17-DQ 24. BW4 controls DQ25-DQ32.
BW1, BW2 , BW3, and BW4 can be active only
with BWE being LOW. GW being LOW causes
all bytes to be written. WRITE pass-through
capability allows written data available at the output for
the immediately next READ cycle. This device also
incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: FEB. 2000
Revision:0.A