T2316160A Datasheet, PDF (1/13 Pages) Taiwan Memory Technology – 1024K x 16 DYNAMIC RAM FAST PAGE MODE

tm TE
CH
DRAM
T2316160A
1024K x 16 DYNAMIC RAM
FAST PAGE MODE
FEATURES
• Industry-standard x 16 pinouts and timing
functions.
• Single 5V (±10%) power supply.
• All device pins are TTL- compatible.
• 1K-cycle refresh in 16ms.
• Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
• BYTE WRITE and BYTE READ access cycles.
OPTION
TIMING
MARKING
45ns
-45
60ns
-60
PACKAGE
42-pin SOJ
J
44/50-pin TSOPII S
PIN ASSIGNMENT ( Top View )
VDD
1
DQ0
2
DQ1
3
DQ2
4
DQ3
5
VDD
6
DQ4
7
DQ5
8
DQ6
9
DQ7
10
NC
11
NC
12
WE
13
RAS
14
NC
15
NC
16
A0
17
A1
18
A2
19
A3
20
VDD
21
42
Vss
41
DQ15
40
DQ14
39
DQ13
38
DQ12
37
Vss
36
DQ11
35
DQ10
34
DQ9
33
DQ8
32
NC
31
CASL
30
CASH
29
OE
28
A9
27
A8
26
A7
25
A6
24
A5
23
A4
22
Vss
GENERAL DESCRIPTION
The T2316160A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316160A has both
BYTE WRITE and WORD WRITE access cycles
via two CAS pins. It offers Fast Page mode with
Extended Data Output.
The T2316160A CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL to transition low in a WRITE cycle will
write data into the lower byte (DQ0~DQ7), and
CASH transiting low will write data into the
upper byte (DQ8~DQ15).
VDD
1
DQ0
2
DQ1
3
DQ2
4
DQ3
5
VDD
6
DQ4
7
DQ5
8
DQ6
9
DQ7
10
NC
11
NC
15
NC
16
WE
17
RAS
18
NC
19
NC
20
A0
21
A1
22
A2
23
A3
24
VDD
25
50
Vss
49
DQ15
48
DQ14
47
DQ13
46
DQ12
45
Vss
44
DQ11
43
DQ10
42
DQ9
41
DQ8
40
NC
36
NC
35
CASL
34
CASH
33
OE
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
Vss
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:A