T224160B Datasheet, PDF (1/14 Pages) Taiwan Memory Technology – 256K x 16 DYNAMIC RAM FAST PAGE MODE

tm TE
CH
DRAM
T224160B
256K x 16 DYNAMIC RAM
FAST PAGE MODE
FEATURES
• Industry-standard x 16 pinouts and timing
functions.
• Single 5V (±10%) power supply.
• All device pins are TTL- compatible.
• 512-cycle refresh in 8ms.
• Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
• Conventional FAST PAGE MODE access cycle.
• BYTE WRITE and BYTE READ access
cycles.
OPTION
TIMING
30ns
35ns
45ns
60ns
MARKING
-30
-35
-45
-60
will write data into the upper byte (IO9~16).
PIN ASSIGNMENT ( Top View )
Vcc 1
I/01 2
I/02 3
I/03 4
I/04 5
Vcc 6
I/05 7
I/06 8
I/07 9
I/08 10
SOJ
NC 11
NC 12
WE 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
Vcc 20
40 Vss
39 I/016
38 I/015
37 I/014
36 I/013
35 Vss
34 I/012
33 I/011
32 I/010
31 I/09
30 NC
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
PACKAGE
SOJ
TSOP(II)
MARKING
J
S
GENERAL DESCRIPTION
The T224160B is a randomly accessed solid state
memory containing 4,194,304 bits organized in a x16
configuration. The T224160B has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode operation
The T224160B CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high during
WRITE will result in a BYTE WRITE. CASL
transiting low in a WRITE cycle will write data into
the lower byte (IO1~IO8), and CASH transiting low
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Vcc
1
I/01
2
I/02
3
I/03
4
I/04
5
Vcc
6
I/05
7
I/06
8
I/07
9
I/08 10
NC 11
NC 12
WE 13
RAS 14
NC 15
A0
16
A1
17
A2
18
A3
19
Vcc 20
TSOP(II)
40
Vss
39
I/016
38
I/015
37
I/014
36
I/013
35
Vss
34
I/012
33
I/011
32
I/010
31
I/09
30
NC
29
CASL
28
CASH
27
OE
26
A8
25
A7
24
A6
23
A5
22
A4
21
VSS
Publication Date: MAR. 2001
Revision:B