TM4C1233H6PGE Datasheet, PDF (998/1261 Pages) Texas Instruments – Tiva Microcontroller

Inter-Integrated Circuit (I²C) Interface
16.1 Block Diagram
Figure 16-1. I²C Block Diagram
Interrupt
I²C Control
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIMR
I2CSRIS
I2CSMIS
I2CSICR
I2CPP
I²C Master Core
I2CSCL
I2CSDA
I²C Slave Core
I2CSCL
I2CSDA
I²C I/O Select
I2CSCL
I2CSDA
16.2
Signal Description
The following table lists the external signals of the I²C interface and describes the function of each.
The I²C interface signals are alternate functions for some GPIO signals and default to be GPIO
signals at reset, with the exception of the I2C0SCL and I2CSDA pins which default to the I²C
function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for the I²C signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL)
register (page 662) should be set to choose the I²C function. The number in parentheses is the
encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL)
register (page 681) to assign the I²C signal to the specified GPIO port pin. Note that the I2CSDA pin
should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 633.
Table 16-1. I2C Signals (144LQFP)
Pin Name
I2C0SCL
Pin Number Pin Mux / Pin
Assignment
99
PB2 (3)
I2C0SDA
I2C1SCL
I2C1SDA
I2C2SCL
I2C2SDA
I2C3SCL
100
PB3 (3)
45
PA6 (3)
51
PG4 (3)
46
PA7 (3)
50
PG5 (3)
59
PF6 (3)
139
PE4 (3)
58
PF7 (3)
140
PE5 (3)
1
PD0 (3)
55
PG0 (3)
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer Type^a Description
OD
I²C module 0 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
OD
I²C module 0 data.
OD
I²C module 1 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
OD
I²C module 1 data.
OD
I²C module 2 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
OD
I²C module 2 data.
OD
I²C module 3 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
998
June 12, 2014
Texas Instruments-Production Data