PCM5141 Datasheet, PDF (99/110 Pages) Texas Instruments – 2VRMS DirectPath™, 112/106dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface

PCM5141, PCM5142
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R2OV
SFOV
Dec
Hex
91
5B
Reset Value
RSV
DTFS[2:0]
DTSR[3:0]
Dec
Hex
92
5C
Reset Value
SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012
1: Overflow occurred
Right2 Overflow (Read Only)
The bit indicates whether the right channel of DSP second output port has overflow. This bit is sticky and is
cleared when read. 0: No overflow
1: Overflow occurred
Shifter Overflow (Read Only)
This bit indicates whether overflow occurred in the DSP shifter (possible sample corruption). This bit is sticky
and is cleared when read. 0: No overflow
1: Overflow occurred
Page 0 / Register 91
b7
b6
b5
b4
b3
b2
b1
b0
RSV
DTFS2
DTFS1
DTFS0
DTSR3
DTSR2
DTSR1
DTSR0
Reserved
Reserved. Do not access.
Detected f_S (Read Only)
These bits indicate the currently detected audio sampling rate. 000: Error (Out of valid range)
001: 8 kHz
010: 16 kHz
011: 32-48 kHz
100: 88.2-96 kHz
101: 176.4-192 kHz
110: 384 kHz
Detected SCK Ratio (Read Only)
These bits indicate the currently detected SCK ratio. Note that even if the SCK ratio is not indicated as error,
clock error might still be flagged due to incompatible combination with the sampling rate. Specifically the SCK
ratio must be high enough to allow enough DSP cycles for minimal audio processing when PLL is disabled. The
absolute SCK frequency must also be lower than 50 MHz. 0000: Ratio error (The SCK ratio is not allowed)
0001: SCK = 32f_S
0010: SCK = 48f_S
0011: SCK = 64f_S
0100: SCK = 128f_S
0101: SCK = 192f_S
0110: SCK = 256f_S
0111: SCK = 384f_S
1000: SCK = 512f_S
1001: SCK = 768f_S
1010: SCK = 1024f_S
1011: SCK = 1152f_S
1100: SCK = 1536f_S
1101: SCK = 2048f_S
1110: SCK = 3072f_S
Page 0 / Register 92
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DTBR8
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: PCM5141 PCM5142
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