TVP3026_09 Datasheet, PDF (96/107 Pages) Texas Instruments – Video Interface Palette

Extended Mode Setup
1. Set loop clock PLL PLLEN bit to 0.
2. Set pixel clock PLL PLLEN bit to 0.
3. Set PLLSEL(1, 0) bits to 1x. (This causes programmed PLLEN bits to take effect. VCOs are
stopped.)
4. Program pixel clock PLL N, M, and P registers (with PLLEN bit = 1) for new frequency.
5. Poll pixel clock PLL status register until LOCK bit is set to 1.
6. Program loop clock PLL Q divider (MCLK/loop clock control register bits 2–0).
7. Program loop clock PLL N, M, and P registers (with PLLEN bit = 1) to new setting.
8. Poll loop clock PLL status register until LOCK bit is set to 1.
Table C–2 TVP3026 Clock Programming Procedure – Extended Mode Setup
Index
Data
Comment
1A
75
Select pixel clock PLL as clock source. Set bits 6–4 to
disable unused VCLK output (see Note 3).
2C
2A
Point to P registers
2F
0
Set loop clock PLL PLLEN bit to 0.
2D
0
Set pixel clock PLL PLLEN bit to 0.
PLLSEL(1, 0)
11
Causes programmed PLLEN bits to take effect. VCOs
are stopped.
2C
0
Point to N registers
2D
N, M, P from table
Program pixel clock PLL (see Note 4)
2C
3F
Point to status registers
2D
(read)
Poll until bit 6 (LOCK bit) is set
39
3X^†
Set Q divider for loop clock PLL
2C
0
Point to N registers
2F
E1, 3D, Fx^† (8 bpp)
Program loop PLL
F1, 3D, Fx (15/16 bpp)
F9, BE, Fx (24 bpp, 8:3 mux)
F9, 3D, Fx (32 bpp)
2C
3F
Point to status registers
2F
(read)
Poll until bit 6 (LOCK bit) is set to 1.
† _{Depends on pixel clock frequency so that the loop clock PLL VCO is within its operating range.}
NOTES: 3. Setting index 0x1A bits 6–4 to 111 for all modes is optional. This disables the unused VCLK output for the
purpose of eliminating unnecessary switching. This changes the value from 0x07 to 0x77 for VGA mode,
and from 0x05 to 0x75 for high-resolution VGA and extended modes.
4. The upper two bits of the N register for all PLLs should be set to 11.
C–2