DP83816AVNG-NOPB Datasheet, PDF (95/109 Pages) Texas Instruments – 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter-II)

7.0 DC and AC Specifications (Continued)
7.2.6 PCI Bus Cycles
The following table parameters apply to ALL the PCI Bus Cycle Timing Diagrams contained in this section.
Number
Parameter
Min
7.2.6.1 ^{Input Setup Time}
7
7.2.6.2 ^{Input Hold Time}
0
7.2.6.3 ^{Output Valid Delay}
2
7.2.6.4 ^{Output Float Delay (t}off ^time)
7.2.6.5 ^{Output Valid Delay for REQN - point to point}
2
7.2.6.6 ^{Input Setup Time for GNTN - point to point}
10
Max
Units
ns
ns
11
ns
28
ns
12
ns
ns
PCI Configuration Read
PCICLK
FRAMEN ^{T1 T2}
AD[31:0]
C/BEN[3:0]
IDSEL
IRDYN
T1 ^T2
T3
Addr
T1 ^T2 _T1
Cmd BE
T1 ^T2
T1
TRDYN
T3
DEVSELN
PAR
T1 ^T2
T3
PERRN
T3
T4
Data
T2
T2
T3
T3
T1
T4
T4
T4
T2
T1
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