TMS320C6203B_15 Datasheet, PDF (93/109 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6203B
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS086N − JANUARY 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 54)
-250
-300
NO.
MASTER
SLAVE
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high
12
5 th(CKXH-DRV) Hold time, DR valid after CLKX high
4
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
2 − 3P
5 + 6P
UNIT
ns
ns
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 54)
NO.
PARAMETER
1 th(CKXH-FXL)
2 td(FXL-CKXL)
Hold time, FSX low after CLKX high¶
Delay time, FSX low to CLKX low#
3 td(CKXL-DXV)
Delay time, CLKX low to DX valid
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
MASTER§
-250
-300
SLAVE
MIN MAX MIN MAX
T−2 T+3
H−2 H+3
−3
4 3P + 4 5P + 17
UNIT
ns
ns
ns
H−2 H+3
ns
7 tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
P + 3 3P + 17 ns
8 td(FXL-DXV)
Delay time, FSX low to DX valid
2P + 2 4P + 17 ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)}
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
The maximum transfer rate for SPI mode is limited to the above AC timing constraints.
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
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