AFE7222_14 Datasheet, PDF (92/107 Pages) Texas Instruments – Analog Front End Wideband Mixed-Signal Transceiver

AFE7222
AFE7225
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
www.ti.com
Therefore fastest update time:
First update = 22*25ns + 40ns = 590 ns
Subsequent update = 12*25ns = 300 ns
For the direct access mode where DAC_A and DAC_B are both written through SDATA, the timing is
shown in figure below.
SCLK
SEN
SDATA
t_PER
TO GET INTO DIRECT ACCESS
MODE
AUX DAC A INPUT1
AUX DAC B INPUT1
01
00
0 1 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4
AUXDAC_A
AUXDAC_B
DELAY FOR FIRST UPDATE = 34 CLOCKS
t_SETTLE
Figure 10-19. Aux DAC Timing Diagram: DAC_A and DAC_B are Both Written Through SDATA
Therefore fastest update time:
First update = 34*25ns + 40ns = 890 ns
Subsequent update = 24*25ns = 600 ns
After the first Aux DAC refresh, subsequent refresh of the Aux DAC outputs in the above mentioned direct
access mode takes place after every 24 clocks. Note that the Aux DAC takes about 12 mA on
AVDD3_AUX (when full scale output is set to 5 mA each Aux DAC).
10.11 Full Duplex Operation – Coupling Considerations
When operating the transmit and receive channels simultaneously, several factors need to be considered
in order to minimize the coupling between the transmit and receive channels. In a general case, the DAC
and ADC clocks can be at arbitrary rates, with or without harmonic relations to each other. In such a case,
there exist serious possibilities of coupling between the ADC and DAC. As far as possible, we recommend
driving the ADC and DAC with the same clock rate externally, and use the internal clock division and
multiplication to adjust to the required ADC and DAC clock rates internally.
The internal block diagram of the clocking path is repeated below.
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