TM4C1230D5PM Datasheet, PDF (918/1103 Pages) Texas Instruments – Tiva™ TM4C1230D5PM Microcontroller

Inter-Integrated Circuit (I²C) Interface
15.3.1.1
START and STOP Conditions
The protocol of the I²C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
15-3.
Figure 15-3. START and STOP Conditions
SDA
SCL
START
condition
STOP
condition
SDA
SCL
The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated
START condition. To generate a single transmit cycle, the I²C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and the Control register is written
with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the
operation is completed (or aborted due an error), the interrupt pin becomes active and the data may
be read from the I²C Master Data (I2CMDR) register. When the I²C module operates in Master
receiver mode, the ACK bit is normally set causing the I²C bus controller to transmit an acknowledge
automatically after each byte. This bit must be cleared when the I²C bus controller requires no further
data to be transmitted from the slave transmitter.
When operating in slave mode, the STARTRIS and STOPRIS bits in the I²C Slave Raw Interrupt
Status (I2CSRIS) register indicate detection of start and stop conditions on the bus and the I²C
Slave Masked Interrupt Status (I2CSMIS) register can be configured to allow STARTRIS and
STOPRIS to be promoted to controller interrupts (when interrupts are enabled).
15.3.1.2
Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 15-4. After the START condition, a slave address
is transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S
bit in the I2CMSA register). If the R/S bit is clear, it indicates a transmit operation (send), and if it
is set, it indicates a request for data (receive). A data transfer is always terminated by a STOP
condition generated by the master, however, a master can initiate communications with another
device on the bus by generating a repeated START condition and addressing another slave without
first generating a STOP condition. Various combinations of receive/transmit formats are then possible
within a single transfer.
Figure 15-4. Complete Data Transfer with a 7-Bit Address
SDA
MSB
LSB
R/S
ACK
MSB
LSB
ACK
SCL
Start
1
2
7
8
9
Slave address
1
2
7
8
9
Data
Stop
The first seven bits of the first byte make up the slave address (see Figure 15-5). The eighth bit
determines the direction of the message. A zero in the R/S position of the first byte means that the
918
June 12, 2014
Texas Instruments-Production Data