DP83640TVV Datasheet, PDF (91/136 Pages) Texas Instruments – DP83640 Precision PHYTER - IEEE 1588 Precision Time Protocol Transceiver

DP83640
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SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013
Table 10-12. PHY Status Register (PHYSTS), address 0x10 (continued)
Bit
Bit Name
2
DUPLEX STATUS
1
SPEED STATUS
0
LINK STATUS
Default
0, RO
0, RO
0, RO
Description
Duplex:
This bit indicates duplex status and is determined from Auto-Negotiation or
Forced Modes.
1 = Full duplex mode.
0 = Half duplex mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and
there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
Speed10:
This bit indicates the status of the speed and is determined from Auto-
Negotiation or Forced Modes.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and
there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
Link Status:
This bit is a duplicate of the Link Status bit in the BMSR register, except that it
will not be cleared upon a read of the PHYSTS register.
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
10.1.11 MII Interrupt Control Register (MICR)
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation
include: Link Quality Monitor, Energy Detect State Change, Link State Change, Speed Status Change,
Duplex Status Change, Auto-Negotiation Complete or any of the counters becoming half-full. The
individual interrupt events must be enabled by setting bits in the MII Interrupt Status and Event Control
Register (MISR).
Table 10-13. MII Interrupt Control Register (MICR), address 0x11
Bit
Bit Name
Default
Description
15:4
RESERVED
0000 0000 0000, RO RESERVED: Writes ignored, read as 0.
3
PTP_INT_SEL
0, RW
PTP Interrupt Select:
Maps PTP Interrupt to the MISR register in place of the Duplex Interrupt. The
Duplex Interrupt will be combined with the Speed Interrupt.
1 = Map PTP Interrupt to MISR[11] , Speed/Duplex Interrupt to MISR[12]
0 = Map Duplex Interrupt to MISR[11], Speed Interrupt to MISR[12]
2
TINT
0, RW
Test Interrupt:
Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will
continue to be generated as long as this bit remains set.
1 = Generate an interrupt.
0 = Do not generate interrupt.
1
INTEN
0, RW
Interrupt Enable:
Enable interrupt dependent on the event enables in the MISR register.
1 = Enable event based interrupts.
0 = Disable event based interrupts.
0
INT_OE
0, RW
Interrupt Output Enable:
Enable interrupt events to signal via the PWRDOWN/INTN pin by configuring the
PWRDOWN/INTN pin as an output.
1 = PWRDOWN/INTN is an Interrupt Output.
0 = PWRDOWN/INTN is a Power Down Input.
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