TUSB4020BI_15 Datasheet, PDF (9/45 Pages) Texas Instruments – TUSB4020BI Two-Port USB 2.0 Hub

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TUSB4020BI
SLLSEI0 – JULY 2015
7.7 Power-Up Timing Requirements
t_d1
t_d2
t_{su_io}
t_{hd_io}
t_{VDD33_RAMP}
t_{VDD_RAMP}
VDD33 stable before VDD stable⁽¹⁾
VDD and VDD33 stable before deassertion of GRSTz
Setup for MISC inputs⁽³⁾ sampled at the deassertion of GRSTz
Hold for MISC inputs⁽³⁾ sampled at the deassertion of GRSTz.
VDD33 supply ramp requirements
VDD supply ramp requirements
MIN
see ⁽²⁾
3
0.1
0.1
0.2
0.2
NOM
MAX
100
100
UNIT
ms
ms
µs
µs
ms
ms
(1) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay
counting from both power supplies being stable to the de-assertion of GRSTz.
(2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must
be stable minimum of 10 μs before the VDD33.
(3) MISC pins sampled at deassertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.
Td2
GRSTz
VDD33
VDD
MI SC _I O
Td1
Tsu_io
Thd_io
Figure 1. Power-Up Timing Requirements
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