TPS65581 Datasheet, PDF (9/28 Pages) Texas Instruments – 4.5V to 18V Input 1.5A, 2.5A, 1.5A Triple Synchronous Step-Down Converter

TPS65581
www.ti.com
SLVSC38A – OCTOBER 2013 – REVISED NOVEMBER 2013
Following are some important considerations for this type of overcurrent protection. The load current one half of
the peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited,
the output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. When the over current condition is removed, the output voltage returns to the regulated value. This
protection is non-latching.
Lower than 1.5 A load current for CH1 and CH3 is required at the V_OUT setting in high on-duty because the
overcurrent limit function causes the degradation of load transient response.
Hiccup Mode
Hiccup mode of operation protects the power supply from being damaged during an ove-current fault condition.
The operation of hiccup is as follows. If the OCL comparator circuit detects an over-current event the output
voltage falls. When the feedback voltage falls below 68% of the reference voltage, the UVP comparator output
goes high and an internal UVP delay counter begins counting. After counting UVP delay time, the TPS65581
shuts off the power supply for a given time (7x UVP Enable Delay Time) and then tries to re-start the power
supply. If the over-load condition has been removed, the power supply starts and operates normally; otherwise,
the TPS65581 detects another overcurrent event and shuts off the power supply again, repeating the previous
cycle. Excess heat due to overload lasts for only a short duration in the hiccup cycle, therefore the junction
temperature of the power devices is much lower.
POWERGOOD
The TPS65581 has power-good output that are measured on VFBx. The power-good function is activated after
the soft-start has finished. If the all output voltages of 3 channels are within 16% of the target voltage, the
internal comparator detects the power good state and the power good signal becomes high after 1.5ms delay.
During start-up, this internal delay starts after 1.5ms of the UVP Enable delay time to avoid a glitch of power-
good signal. Even if at least one of the feedback voltages of 3 channels goes outside of ±16% of target value,
the power-good signal becomes low after 2 µs.
<Start up>
Figure 1. Start up
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