TPA3245 Datasheet, PDF (9/28 Pages) Texas Instruments – 200W Mono PurePath Ultra-HD Analog-Input

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TPA3245
SLASEC7 – APRIL 2016
level. If the maximum output current persists, i.e. the power stage being overloaded with too low load impedance,
the device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z)
state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an over current
event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning of next
PWM frame.
PWM_X
HS PWM
RISING EDGE PWM
SETS CB3C LATCH
LS PWM
OUTPUT CURRENT
OC THRESHOLD
OC EVENT RESETS
CB3C LATCH
OCH
HS GATE-DRIVE
LS GATE-DRIVE
Figure 2. CB3C Timing Example
During CB3C an over load counter increments for each over current event and decrease for each non-over
current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown
protection action. In the event of a short circuit condition, the over current protection limits the output current by
the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum
value. If a latched OC operation is required such that the device shuts down the affected output immediately
upon first detected over current event, this protection mode should be selected. The over current threshold and
mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be
within its intentional value range for either CB3C operation or Latched OC operation.
I_OC
IOC_max
IOC_min
Not Defined
ROC_ADJ
Figure 3. OC Threshold versus OC_ADJ Resistor Value Example
OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC
threshold.
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