TNETE211 Datasheet, PDF (9/15 Pages) Texas Instruments – ThunderLANE TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN

TNETE211
ThunderLAN™ TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR
100VG-AnyLAN
SPWS019 – MAY 1995
MII receive timing requirements^†
PARAMETER
tsu(MTx _pins) Setup time of inputs MTXD[0–3], MTXEN, MTXER (see Note 4)
th(MTx _pins) Hold time of inputs MTXD[0–3], MTXEN, MTXER (see Note 4)
MIN MAX UNIT
10
ns
>0
ns
MII transmit switching characteristics^†
PARAMETER
MIN MAX UNIT
td(MRx _pins) MRCLK to output delay for MRXD[0–3], MRXDV, and MRXER (see Note 5)
0
15 ns
† _{Both MCRS and MCOL are driven asynchronously by the PMI.}
NOTES: 4. MTXD[0–3] is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and deasserted by the
reconciliation sublayer synchronous to the MTCLK rising edge. MTXER is driven synchronous to the rising edge of MTCLK.
5. MRXD[0–3] is driven by the PMI on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the edge
of MRCLK. MRXD[0–3] timing must be met during clock periods where MRXDV is asserted. MRXDV is asserted and deasserted
by the PMI on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising edge of MRCLK.
MRXER is driven by the PMI on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising
edge of MRCLK. MRXER timing must be met during clock periods when MRXDV is asserted.
MRCLK
MRXD[0–3],
MRXDV,
MRXER
td(MRx _pins)
MTCLK
MTXD[0–3],
MTXEN,
MTXER
tsu(MTx _pins)
th(MTx _pins)
Figure 3. MII Transmit and Receive Timing
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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