TLV1549 Datasheet, PDF (9/19 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL

TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C – JANUARY 1993 – REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range,
V_CC = V_ref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz
PARAMETER
TEST CONDITIONS MIN MAX UNIT
Linearity error (see Note 6)
± 1 LSB
Zero error (see Note 7)
See Note 2
± 1 LSB
Full-scale error (see Note 7)
See Note 2
± 1 LSB
Total unadjusted error (see Note 8)
± 1 LSB
tconv
tc
Conversion time
Total cycle time (access, sample, and conversion)
See Figures 6 – 11
See Figures 6 – 11
and Note 9
21
μs
21
+ 10 I/O
CLOCK
μs
periods
tv
Valid time, DATA OUT remains valid after I/O CLOCK↓
See Figure 5
10
ns
td(I/O-DATA) Delay time, I/O CLOCK↓ to DATA OUT valid
See Figure 5
240
ns
tPZH, tPZL Enable time, CS↓ to DATA OUT (MSB driven)
See Figure 3
1.3
μs
tPHZ, tPLZ Disable time, CS↑ to DATA OUT (high impedance)
See Figure 3
180
ns
tr(bus)
Rise time, data bus
See Figure 5
300
ns
tf(bus)
Fall time, data bus
See Figure 5
300
ns
td(I/O-CS) Delay time, 10th I/O CLOCK↓ to CS↓ to abort conversion (see Note 10)
9
μs
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF – convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref ₊ – Vref _–); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A / D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven
I/O CLOCK periods, and ends on the falling edge of the tenth I/O CLOCK (see Figure 5).
10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the internal clock (1.425 μs) after the transition.
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