PT6460_14 Datasheet, PDF (9/12 Pages) Texas Instruments – 14 A Output Current

Application Notes
PT6460 & PT6470 Series
Using the Inhibit Control of the PT6460 & PT6470
Series of Step-Down ISRs
The PT6460 (5-V input) and the PT6470 (3.3-V input)
series of integrated switching regulators (ISRs) provide
step-down voltage conversion for output loads of up to
14 A. For applications that require the output voltage
to be held off, these ISRs incorporate an Inhibit* control
(pin 1). The Inhibit* control input can be used for power-
up sequencing or whenever there is a requirement for
the output voltage from the ISR to be turned off.
The ISR functions normally with pin 1 open circuit,
providing a regulated output whenever a valid source
voltage is applied between V_in (pins 2–3) and GND (pins
5–8). When a low-level ground signal is applied to pin 1,
the regulator output is turned off ² and the input current
is significantly reduced ³.
Figure 4-1 shows the typical application of the Inhibit*
function. Note the discrete transistor, Q₁. The Inhibit*
control has its own internal pull-up to V_in potential. An
open-collector or open-drain device is recommended to
control this input ¹. The voltage thresholds are given in
Table 4-1.
Table 4-1; Inhibit Control Requirements
Parameter
Enable (VIH)
Disable (VIL)
I IL
Min
Typ
Vin – 0.5 V
–0.2 V
—
—
—
–0.2 mA
Max
Open
+0.8 V
—
Turn-On Time: In the circuit of Figure 4-1, turning Q₁ on
applies a low-voltage to the Inhibit* control (pin 1) and
disables the output of the regulator ². If Q₁ is then turned
off, the ISR executes a soft-start power up. Power up
consists of a short delay (approx. 2 msec), followed by a
period in which the output voltage rises to the full regu-
lation voltage. The module produces a regulated output
voltage within 10 msec. Figure 4-2 shows the typical rise
in both the output voltage and input current for a PT6464
(1.8 V), following the turn-off of Q₁. The turn off of Q₁
corresponds to the rise in the waveform, Q₁ V_ds. The
waveforms were measured with a 5VDC input voltage,
and 8.5-A load.
Figure 4-2
HORIZ SCALE: 2ms/Div
Vo (1V/Div)
Iin (2A/Div)
Q1Vds (5V/Div)
Figure 4-1
+V_IN
2–4 _Vin
11
+Vsense
+V_SENSE
PT6464
Vout ^9–10
V_OUT
Inhibit*
1
GND
5–8
Vo(adj)
12
C_IN
+
560 µF
(Req'd)
1 =Inhibit
Q₁
BSS138
C_OUT
+
330 µF
L
O
(Optional)
A
D
COM
GND
Notes:
1. Use an open-collector device with a breakdown voltage
of at least 10 V (preferably a discrete transistor) for the
Inhibit* control input. A pull-up resistor is not necessary.
To disable the output voltage the control pin should be
pulled low to less than +0.8 VDC.
2. When a ground signal is applied to the Inhibit* control
(pin 1) the module output is effectively turned off (tri-
state). The output voltage decays to zero as the load
impedance discharges the output capacitors.
3. When the output is disabled via the Inhibit* pin, the
input current is reduced to approximately 5 to 10 mA.
For technical support and more information, see inside back cover or visit www.ti.com